The BEEcube Platform Studio (BPS) is a system-level, hardware/software, co-development environment on top of the MathWorks™ Simulink® framework. BPS provides automatic generation of all platform specific hardware interfaces and corresponding software drivers, and a direct algorithm to implementation conversion without requiring user knowledge of the low level implementation details.

What is a Platform?

Each BPS platform is a collection of hardware devices and associated software available on the physical module. The BPS platform has been purpose-built to abstract hardware specific details away from the end user.

The smallest unit of the BPS platform is a single FPGA.

A typical design in the BPS design environment starts with the core algorithm design in Simulink with Xilinx System Generator for DSP. From the end-user perspective, Simulink designs only exist in an idealized sandbox with the synchronous data flow execution model; all connections outside the core algorithm are virtually mapped through BPS interface block sets.
Click for a larger image.

A processor core, either in the form of a hard core (PowerPC 405) or soft core (MicroBlaze™ processor), is implicitly included in all BPS designs. The processor core can communicate with the user XSG design through software registers, FIFO, or shared memory. Users can specify the desired communication method by selecting the corresponding BPS blocks in Simulink. All external network, I/O, and memory devices are abstracted into Simulink data sources or sinks, with a simple FIFO abstraction.

For each of the supported FPGA board platforms, BPS framework provides a base system package as a complete Xilinx Platform Studio (XPS) project, and the corresponding Simulink BPS block set for all the external devices. Each base-system package includes the essential system device IP cores, initial hardware system configuration, and available software packages.
Click for a larger image.

The back-end implementation files for the user-selected external devices are dynamically generated by the BPS tools on top of the base package. These are then combined and linked with all necessary hardware connections and software device drivers.

Base PackageClick for a larger image.

The base BPS package is a preconfigured Embedded Development Kit (EDK) project to be applicable generally for the specific BPS platform with minimal hardware and software configuration. Typically, there is one base package per FPGA in the system with minimal configurations including ...

• A single embedded microprocessor core (i.e., PowerPC or MicroBlaze) per FPGA for system integration, management, and debugging
• Minimal system devices such as UART and Ethernet
• A minimal user software debugging shell, such as TinySH
• At least one static clock source, such as a 100MHz crystal

BPSLibrary Blocks & IP
BPS uses a Simulink-based blockset for each platform group in order to abstract away the low level hardware implementation and software device driver details. These blocks range from simple interfaces, such as GPIO, Software Register, Shared BRAM, to more complex devices, such as multi-port external SRAM/DRAM memory controller, 10 Gigabit network interfaces, and PCI Express DMA engines.

3rd Party Software Requirements

• MathWorks MATLAB/Simulink 2007b
• Xilinx ISE 10.1i SP2
• Xilinx EDK 10.1i SP2
• Xilinx System Generator 10.1i SP2